Design a 16x1 Multiplexer Using 4x1 Multiplexers
Data Transmission in Communication Systems and Boolean Logic Implementation
A multiplexer (abbreviated as MUX) is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines.
Block Diagram of a 2:1 MUX
Normally. there are 2^n input lines and n selection lines whose bit combinations determine which input is selected.
A multiplexer can be visualized as a data router which routes data from one of multiple input lines (determined by select lines) to a single output line. This can be used in communication systems to transmit multiple signals using a single channel (transmission link).
MUX can be implemented using Logic gates such as AND,OR,NAND etc. or Transmission gates (Tristate Buffers).
A demultiplexer (abbreviated as DEMUX) performs the reverse operation of a multiplexer. It routes data from a single input line to one of multiple output lines (determined again by select lines).
Block Diagram of a 1:2 DEMUX
A Communication System making use of MUX and DEMUX
Timing Diagram of a 4:1 MUX
When S1S0 = 00, D0 is selected (00 is the binary representation of 0)
When S1S0 = 01, D1 is selected (01 is the binary representation of 1)
When S1S0 = 10, D2 is selected (10 is the binary representation of 2)
When S1S0 = 11, D3 is selected (11 is the binary representation of 3)
Design of 2:1 MUX:
A 2:1 MUX has two input lines (I0 and I1), one output line (Y) and one select line (S).
If S=0, Y=I0 and if S=1, Y=I1
Truth Table of 2:1 MUX
From the truth table, the Boolean expression for the output of 2:1 MUX can be obtained as:
A 2:1 MUX can be implemented using two 2-input AND gates (1 7408 IC), one 2-input OR gate (1 7432 IC) and one inverter (1 7404 IC)
NAND Logic Implementation
Tristate buffers have a normal input, an output, and a control input that determines the state of the output. When the control input is equal to 1, the output is enabled and the gate behaves like a conventional buffer with the output equal to the normal input. When the control input is 0, the output is disabled and the gate goes to a high-impedance state (the tristate buffer becomes an open circuit), regardless of the value in the normal input. Due to the presence of the high impedance state, the output of several tristate buffers can be tied together to form a common line without any loading effects.
Behavior of a Tristate Buffer
Implementation of 2:1 MUX using Tristate Buffers
Code for Verilog HDL Simulation:
module mux_2x1_case(i0,i1,s0,out); input i0,i1,s0; output reg out; always @(*) begin case(s0) 1 'b0:out=i0; 1' b1:out=i1; endcase; end endmodule
Simulated waveforms for a 2:1 MUX
Design of 4:1 MUX:
A 4:1 MUX has four input lines (I0,I1,I2 and I3), one output line (Y) and two select lines (S1 and S0).
Truth Table of 4:1 MUX
From the truth table, the Boolean expression for the output of 4:1 MUX can be obtained as:
A 4:1 MUX can be implemented using four 3-input AND gates (2 7411 IC), three 2-input OR gates (1 7432 IC) and two inverters (1 7404 IC).
NAND Logic Implementation
Tristate Buffer Implementation
The 2 by 4 decoder gives the outputs S1'S0' , S1'S0 , S1S0' , S1S0 which are then given as the control signals to the tristate buffers to select the desired input.
A 4:1 MUX can also be implemented using three 2:1 MUXes. Here s1 and s0 are select lines and w0, w1, w2 and w3 are the input lines.
Code for Verilog HDL Simulation:
module mux_4x1_case(i0,i1,i2,i3,s,out); input i0,i1,i2,i3; input [1 : 0]s; output reg out; always @(*) begin case(s) 2 'b00:out=i0; 2' b01:out=i1; 2 'b10:out=i2; 2' b11:out=i3; endcase end endmodule
Simulated waveforms for a 4:1 MUX
Implementation of Boolean Functions using MUX:
A n-variable Boolean Function can be implemented easily using a 2^n : 1 MUX
For example, consider the following truth table
This function can be easily implemented using a 16:1 MUX. The 4 inputs A,B,C and D should be given as the 4 select lines of the MUX.
For the input combination ABCD = 0, the input selected by the MUX is I0. From the truth table we can deduce that I0 = 1. Similarly, the other inputs are given to the MUX.
Implementation of the given 4 variable Boolean Function using 16:1 MUX
However, this is inefficient as the MUX logic complexity increases as number of select lines increases (compare the implementation of 2:1 MUX and 4:1 MUX). So we try to reduce the number of select lines.
A n variable boolean function can be implemented with a 2^(n-1):1 MUX and one inverter.
Consider the 4 variable function specified before, it can be implemented using an 8:1 MUX and an inverter. Three of the inputs, A,B and C in that order are given as the select lines. The input values are determined from the truth table, as a function of the fourth input D.
For a particular combination of input values ABC, D can take two values D=0 and D=1. The Boolean function can also take two values f=0 and f=1. 4 different situations arise for a particular combination of ABC values.
XXX - indicates a particular combination of ABC values (ranging from 000 to 111)
Here f is zero irrespective of the value of D.
Hence for the particular combination of ABC, f = 0
Here f has the same value as D.
Hence for the particular combination of ABC, f = D
Here f is the complement of D.
Hence for the particular combination of ABC, f = D'
Here f is one irrespective of the value of D.
Hence for the particular combination of ABC, f = 1
The Truth table for the 4 variable Boolean function specified above, could be redrawn as:
Implementation of a 4 variable Boolean Function using a 3:1
If we try to reduce the selection lines further, some extra logic gates might be introduced.
An efficient implementation of a n variable Boolean function can be done using a 2^(n-1) : 1 MUX and an inverter.
Design of 1:2 DEMUX:
A 1:2 DEMUX has one input line (I), two output lines (Y1 and Y2) and one select line (S).
If S=0, Y0=I and Y1=0; if S=1, Y0=0 and Y1=I
Truth Table of a 1:2 DEMUX
The Boolean expressions for the outputs Yo and Y1 can be given as
A 1:2 DEMUX can be implemented using two 2-input AND gates (1 7408 IC), and one inverter (1 7404 IC)
Code for Verilog HDL Simulation:
module demux_1x2_cond(I,s0,out); input I,s0; output [1 : 0]out; assign out[0]=s0?1 'b0:I assign out[1]=s0?I:1'b0 endmodule
Simulated waveforms for a 1:2 DEMUX
Design of 1:4 DEMUX:
A 1:4 DEMUX has one input line (I), four output lines (Y0,Y1,Y2 and Y3) and two select lines (S1 and S0).
Truth table of 1:4 DEMUX
The Boolean expressions for the outputs Y0, Y1, Y2 and Y3 can be given as
A 1:4 DEMUX can be implemented using four 3-input AND gates (2 7411 ICs), and two inverters (1 7404 IC)
Code for Verilog HDL Simulation:
module demux_1x4_cond(I,s,out ); input I; input [1:0]s; output [3:0]out; assign out[0]=s[0]?1 'b0:(s[1]?1'b0:I); assign out[1]=s[0]?(s[1]?1 'b0:I):1'b0; assign out[2]=s[0]?1 'b0:(s[1]?I:1'b0); assign out[3]=s[0]?(s[1]?I:1 'b0):1'b0; endmodule
Simulated waveforms for a 1:4 DEMUX
A decoder with an enable input can act as a DEMUX. Since both decoder and demultiplexer operations are obtained from the same circuit, a decoder with an enable input is referred to as a decoder-demultiplexer. This will be dealt with in detail in the next article about the design of Encoders and Decoders.
References:
- M. Morris Mano, Michael D. Ciletti, "Digital Design", 4th Edition
- Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design
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Design a 16x1 Multiplexer Using 4x1 Multiplexers
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